在網上搜到的，應該還不是很全吧，歡迎補充:89) se draw the transistor level schematic of a cmos 2 input AND gate and explain which input has faster response for output rising edge.(less delay time)se show the CMOS inverter schmatic,layout and its cross sectionwith P-well its transfer curve(Vout-Vin) And also explainthe operation region of PMOS and NMOS for each segment of the transfercurve? design a CMOS invertor with balance rise and fall time,please define the ration of channel width of PMOS and NMOS and explain?se draw schematic of a common SRAM cell with 6 transistors,point out which nodes can store data and which node is word linecontrol?se explain how we describe the resistance in semiconductorCompare the resistance of a metal,poly and diffusion in tranditionalCMOS process.
